1. Field of the Invention
The present invention generally relates to semiconductor devices, methods for their fabrication and, more particularly, to three-dimensional semiconductor device structures and methods of providing sub-micron device structures.
2. Description of the Prior Art
The technology of producing semiconductor devices having greater and greater densities has advanced to the sub-micron realm of structural dimensions and is now approaching physical limits in the nanometer (nm) feature size range. In the foreseeable future, absolute atomic physical limits will be reached in the conventional two-dimensional approach to semiconductor device design used to produce Very Large Scale Integrated (VLSI) circuits. Traditionally, Dynamic Random Access Memory (DRAM) designers have faced the severest of challenges in advancing the technology. For example, designers of 64K DRAMs were confronted with the fact that a practical physical limit to charge capacity of storage capacitors had already been reached due to the minimum charge necessary to sense signals in the presence of environmental particulate radiation inherently present in fabrication materials. Storage capacitors in the range of 50 femto Farads (fF or 10.sup.-15 Farads) are now considered to be a physical limit. From a practical view, this limitation prevented the scaling of DRAM capacitors. Reduction of the surface area of a semiconductor substrate utilized by the storage capacitor has been severely restricted. Due to decreases in the thickness of capacitor materials, existing one Megabit (1 Mb) DRAM technologies continue to enjoy a freedom of planar device in circuit design. However, beginning with 4 Mb DRAMs the world of three-dimensional design has been explored to the extent that the simple single device/capacitor memory cell has been altered to provide the capacitor in the vertical dimension. In such designs, the capacitor has been formed in a trench in the surface of the semiconductor substrate. In yet denser designs, other forms of capacitor designs are proposed, such as stacking the capacitor above the transfer device. Additional designs have been proposed in which the device and its associated capacitor are formed within a trench of preferably minimum dimension.
While such design approaches appear to allow progressive increases in density in the near future, they are constrained by the limit of one memory cell per minimum photolithographic dimension. If semiconductor technology is to be extendable, design and process techniques are required which will enable true three-dimensional circuit design in which structural features are measured in nm and multiple circuit features are provided in the vertical dimension.